here are the (good) lock parameters used this morning.

for the RF/FPC lock, the 33MHz beating signal used to select the right bucket is 1Vpp
=> beating signal : V0 . sin(phi) with V0=0.5V.

to discrimate a 500MHz bucket, we need to get dV < V0 dphi.

dphi = 2pi / 15 = 420 mrad => dV < 0.2 V => dV < +/- 0.1V

we used dV = +/- 0.02V but perharps we can relax the constraint.

we also reduced the RF scanning speed at 0.1V/s to let the system find the right phase when the system is slowly drifting.